A dynamic access memory array is typically constituted by a plurality of memory cells. FIG. 1 illustrates a schematic structural view of a single memory cell 100 including a transistor 110 and a capacitor 120, wherein the gate of the transistor 110 is controlled by a word line 130. When the word line 130 is enabled, the transistor 110 is conducted to transmit the charges stored in the capacitor 120 to a bit line 140 for a sensing circuit (not shown) connected to the bit line 140 to determine the logic value stored in the memory cell to be 1 or 0. In the entire memory array, a plurality of memory cells is connected to the word line 130, while a plurality of memory cells is also connected to the bit line 140.
However, a memory array generally includes a considerably large amount of memory cells, and some of the memory cells may have defects and inevitably fail. Therefore, a primary memory array is typically provided with a redundant memory array for replacing the defected memory cells. FIG. 2 illustrates a schematic view of a conventional memory array, which includes a primary memory array 200, a redundant word line memory array 210, and a redundant bit line memory array 220. When a memory cell 202 in the primary memory array connected to the N word line 230 and the M bit line 240 fails, one row in the redundant word line memory array 210 can be selected to replace the memory cells connected to the N word line 230, or one column in the redundant bit line array 220 can be selected to replace the memory cells connected to the M bit line 240. Therefore, the failed memory cell 202 can be replaced without affecting the performance of the memory array 200.
During the wafer test stage, when a memory cell is found defected, the test operator may selectively replace the defected memory cell with a redundant word line memory array or a redundant bit line memory array. However, when any cross-fail occurs in a dynamic access memory device, the method described above may not be effective. For example, FIG. 3 illustrates a schematic cross-sectional view of a memory cell 300 suffered from cross-fail, which includes a gate electrode 310, a capacitor 320, and a bit line 340. The gate electrode 310 of the memory cell 300 is formed with a protrusion 305 due to process errors, such as imperfect etching. The protrusion 305 may cause a capacitive connection between the gate electrode 310 and the bit line 340. This kind of failure may be found during the wafer test stage and the tested memory cell is so marked, and then a redundant word line memory array or a redundant bit line memory array may be used to amend the failure.
However, after applying high temperature, high voltage stresses on the memory array with the capacitive connection type failure, the gate electrode 310 and the bit line 340 may be short. In such a case, if a redundant word line array is used to compensate the failure, i.e. even if the memory cell 300 is replaced, the bit line 340 is still practically short with the gate electrode 310. Therefore, in addition to the memory cell 300, other memory cells connected to the bit line 340 are still remained defected.
Therefore, there is a desire to provide a method for testing a dynamic access memory device, which can identify a cross-fail and compensate the fail with a redundant bit line memory array.